(China (Mainland))
Product Summary
The MT48LC16M16A2P-7E is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quadbank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits.
Parametrics
Absolute maximum ratings: (1)Voltage on VDD, VDDQ Supply; (2)Relative to VSS: -1V to +4.6V; (3)Voltage on Inputs, NC or I/O Pins Relative to VSS: -1V to +4.6V; (4)Operating Temperature, TA (commercial): 0°C to +70°C; (5)Operating Temperature,TA (industrial “IT”): -40°C to +85°C; (6)Storage Temperature (plastic): -55°C to +150°C; (7)Power Dissipation: 1W.
Features
Features: (1)Fully synchronous; all signals registered on positive edge of system clock; (2)Internal pipelined operation; column address can be changed every clock cycle; (3)Internal banks for hiding row access/precharge; (4)Programmable burst lengths: 1, 2, 4, 8, or full page.
Diagrams
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 MT48LC16M16A2P-7E IT:D |
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IC SDRAM 256MBIT 133MHZ 54TSOP |
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MT48LC16M16A2P-7E IT:D TR |
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IC SDRAM 256MBIT 133MHZ 54TSOP |
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MT48LC16M16A2P-7E L:D TR |
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IC SDRAM 256MBIT 133MHZ 54TSOP |
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MT48LC16M16A2P-7E L:D |
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IC SDRAM 256MBIT 133MHZ 54TSOP |
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MT48LC16M16A2P-7E:D TR |
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IC SDRAM 256MBIT 133MHZ 54TSOP |
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MT48LC16M16A2P-7E:D |
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IC SDRAM 256MBIT 133MHZ 54TSOPII |
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