EPM7064LC68-15

High-performance, EEPROM-based programmable logic device, PLCC-68, 5ns

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PartNumber:: EPM7064LC68-15

Brand:: Altera Corporation - ALTR | Pack: PLCC | D/C: 09+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-10-06

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Product Summary

The EPM7064LC68-15 is a high-density, high-performance PLD. The EPM7064LC68-15 is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7064LC68-15 provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. It is in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification.

Parametrics

EPM7064LC68-15 absolute maximum ratings: (1)Supply voltage:–2.0 to 7.0V; (2)DC input voltage:–2.0 to 7.0V; (3)DC output current, per pin:–25 to 25mA; (4)Storage temperature:–65℃ to 150℃; (5)Ambient temperature:–65℃ to 135℃; (6)Junction temperature:150℃ or 135℃.

Features

EPM7064LC68-15 features: (1)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (2)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (3)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (4)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (5)PCI-compliant devices available; (6)Open-drain output option in MAX 7000S devices; (7)Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls; (8)Programmable power-saving mode for a reduction of over 50% in each macrocell; (9)Configurable expander product-term distribution, allowing up to 32 product terms per macrocell; (10)Six pin- or logic-driven output enable signals; (11)Two global clock signals with optional inversion; (12)Enhanced interconnect resources for improved routability; (13)Fast input setup times provided by a dedicated path from I/O pin to macrocell registers; (14)Programmable output slew-rate control.